1. Field of the Invention
The present invention relates to a MOS-type charging circuit, and more particularly to a MOS-type charging circuit for charging a large-capacity load in a semiconductor chip having a supply voltage-lowering circuit for converting inside the semiconductor chip an external supply voltage applied from a power supply outside the semiconductor chip to an internal supply voltage which is lower than the external supply voltage.
2. Description of the Related Art
In recent years, in conjunction with the development of semiconductor technology, particularly the development of fine pattern technology, the tendency toward an ever-finer pattern has become more and more pronounced in the field of semiconductor memories as well. For this reason, in view of the reliability of the devices, it is desirable to lower supply voltages that are applied to the devices.
However, for the users who have configured various systems by using semiconductor memories currently in use, if consideration is given to compatibility with the current systems, it is desirable that even if the degree of integration of the semiconductor memories is further increased, external supply voltages V.sub.cc (EXT) applied from outside the chips can be used as they are.
For this reason, development is underway of technology for lowering the voltage applied to the device to a level lower than an external voltage by providing a supply voltage-lowering circuit inside the chip.
In a synchronous-type MOS memory, operations of charging and discharging a large-capacity load inside the chip are frequently carried out. For instance, in charging and discharging operations of a dynamic random-access memory (DRAM), the amount of current itself flowing across each sense amplifier connected to the transistor of each memory cell is small.
In practice, however, there are many cases where, as shown in FIG. 7(a), a load circuit 22 having a multiplicity of sense amplifiers 24 is connected via a driver transistor Q30 to one supply voltage-lowering circuit 20 connected to an external power supply (V.sub.cc (EXT)). In such a case, even though the amount of current itself flowing across one sense amplifier 24 may be small, the current flowing across the driver transistor Q30 instantaneously becomes large. Consequently, the operation of the voltage-lowering circuit 20 cannot sufficiently follow the operation of the load circuit 22, so that an internal supply voltage V.sub.cc (INT) which is an output of the voltage-lowering circuit 20 becomes temporarily unstable.
As shown in FIG. 7(b), this voltage-lowering circuit 20 comprises a differential amplifier 23s for comparing a potential V1 obtained by dividing the internal supply voltage V.sub.cc (INT) of the chip with resistors R30, R31 with a reference potential V.sub.refl which is not dependent on the external supply voltage V.sub.cc (EXT), and also comprises a p-channel MOS transistor Q32 having a gate terminal connected to an output terminal N30 of the differential amplifier 23s. It is so configured that the voltage of the external power supply (V.sub.cc (EXT)) connected to a source terminal of the p-channel MOS transistor Q32 is lowered to a desired voltage of the internal power supply (V.sub.cc (INT)). Here, values of the resistors R30, R31 are set in such a manner that the potential V1 obtained by dividing the potential of the internal supply voltage V.sub.cc (INT) of the chip with the resistors R30, R31 becomes equal with the reference potential V.sub.refl.
More specifically, when the power has been consumed by the load circuit 22 inside the chip, including the sense amplifiers 24, and the potential V1 has dropped below the reference potential V.sub.refl, the p-channel MOS transistor Q32 turns on, and when the internal supply voltage V.sub.cc (INT) has reached a design value, the p-channel MOS transistor Q32 turns off, so as to maintain the internal supply voltage V.sub.cc (INT) at a constant level.
In addition, an output of the voltage-lowering circuit 20 whose voltage has been lowered to a desired internal supply voltage V.sub.cc (INT) is connected to a source terminal of the driver transistor Q30, so that, at the time of sensing, the load circuit 22 is charged up to a desired charging potential (e.g., 2/3 V.sub.cc (EXT)) by the driver transistor Q30.
In order to charge the large-capacity load 22 by using an internal circuit thus configured, since a large current
flows from the external power supply (V.sub.cc (EXT)) through the two p-channel transistors Q30, Q32 connected in series, dimensions of the p-channel transistors Q30, Q32 must be enlarged. Hence, there has been a problem in that this leads to an increase in the chip area.
Meanwhile, the internal power supply (V.sub.cc (INT)) also serves as a power supply for a peripheral circuit 21 which is constituted by an address buffer, a decoder, etc. Consequently, as described above, when charging such a large-capacity load, the current flowing across the driver transistor Q30 instantaneously becomes large, so that the operation of the voltage-lowering circuit is unable to sufficiently follow the operation of the load circuit. Hence, when the internal supply voltage V.sub.cc (INT), which is the output of the voltage-lowering circuit 20, has become temporarily unstable, the operation of the peripheral circuit 21 is affected substantially, thereby causing a malfunctioning of the memory and a drop in an operational margin.
Furthermore, there has been an additional problem in
that when the internal supply voltage V.sub.cc (INT) undergoes large fluctuations due to the driving of a large-capacity load, the operation of the voltage-lowering circuit itself becomes unstable.
Thus, with semiconductor chips using conventional supply voltage-lowering circuits, at the time of charging a large-capacity load, the fluctuations of the internal supply ( voltage V.sub.cc (INT) inside the chip and an increase in the chip area due to the use of two transistors connected in series have been a major problem in hampering the creation of a fine pattern and the improvement of reliability of the device.